package device

import chisel3._
import chisel3.util._
import common.Constants._
import bus._

class MMIO extends Module {
  val io = IO(new Bundle(){
    //val in = Flipped(new AXI4)
    val in = Flipped(new CoreLinkIO(XLEN))
  })

  // mmio, port
  val devAddrSpace = List(
    (0x10000000L, 0x10L),
  //(0x40600000L, 0x10L), // uart
  )

  //device
  val uart = Module(new AXI4UART)


  val xbar = Module(new CoreLinkIOCrossbar1toN(devAddrSpace))
  xbar.io.in <> io.in

  uart.io.in <> xbar.io.out(0).toAXI4Lite()

  //uart.io.in <> io.in
}
